View L8574D_2114502.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet october 1998 L8574D resistive subscriber line interface circuit (slic), ring relay, and protector (srp) for long loop and tr-57 applications features n low-power scan mode for low on-hook power dis- sipation (55 mw max) n low active power dissipation; talk or on-hook transmission (240 mw max) n distortion-free on-hook transmission n eight operating states via latched paralleled data inputs with channel select feature n precision ?ed 28 ma current limiter n integrated protection n no external protection device required n integrated ringing access relay n ring trip detector n loop closure detector with hysteresis n relay driver n battery noise cancellation n thermal protection n 44-pin, surface-mount, plastic package (plcc) description the l8574 is a resistive subscriber line interface cir- cuit (slic) that is optimized for long loop applica- tions, such as bellcore tr-nwt-000057 requirements for digital loop carrier (dlc) applica- tions. it interfaces the low-voltage circuits on an ana- log line card to the tip/ring subscriber loop. the l8574 does not supply dc current to the subscriber loop; external resistors are used for this purpose. included in the l8574 are a solid-state ringing access switch and a line break switch. also included is a relay driver for an external (test) access mechan- ical relay. state control is via four latched parallel data inputs. a chip select feature allows the user to enable, disable, or reset the data latches to a known logic state. the l8574 offers a low-power scan state to minimize power to less than 55 mw in the on-hook state. the l8574 also supports on-hook transmission. the active power in both the talk or on-hook transmission mode is also very low (<240 mw). current is limited to a ?ed value of 25 ma by an internal precision current-limit circuit. because of the internal architecture of the l8574 slic and because of the power rating of the associ- ated external feed resistors, the l8574 will meet most surge requirements without use of an external sec- ondary protection device. internal circuitry steers both positive and negative faults to fault ground. neg- ative faults are not dumped into battery. the l8574 is a two-chip line interface solution pack- aged in a single, 44-pin plcc package. the tip and ring drive ampli?rs, the xmt ampli?r, the receive interface, and battery noise cancellation circuits are fabricated in a 90 v complementary bipolar (cbic) process. the ring access switch, line break switch, battery switch, current-limit, protection functions, supervision, and control functions are fabricated in a 320 v dielectrically isolated bipolar-cmos-dmos (bcdmos) process. the device is available in a 44-pin plcc package.
2 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring table of contents contents page features .................................................................................................................................................................... 1 description ................................................................................................................................................................ 1 architectural diagram ................................................................................................................................................ 4 pin information .......................................................................................................................................................... 4 absolute maximum ratings....................................................................................................................................... 6 electrical characteristics ........................................................................................................................................... 7 ring trip detector ................................................................................................................................................... 8 battery feed ........................................................................................................................................................... 8 fault protection ....................................................................................................................................................... 9 transmission characteristics ................................................................................................................................ 13 data interface and logic....................................................................................................................................... 14 switch characteristics........................................................................................................................................... 15 operating states...................................................................................................................................................... 16 scan state ............................................................................................................................................................ 16 disconnect state................................................................................................................................................... 17 alternate talk state ............................................................................................................................................... 17 talk state .............................................................................................................................................................. 17 scan current-limit state....................................................................................................................................... 17 ringing state ........................................................................................................................................................ 17 on-hook transmission state ................................................................................................................................ 17 intermediate talk state ......................................................................................................................................... 18 applications ............................................................................................................................................................. 18 general ................................................................................................................................................................. 18 resistor module .................................................................................................................................................... 22 protection.............................................................................................................................................................. 24 tip/ring drivers .................................................................................................................................................... 25 receive interface .................................................................................................................................................. 25 transmit interface.................................................................................................................................................. 25 battery noise cancellation ................................................................................................................................... 25 on-hook transmission.......................................................................................................................................... 26 parallel data interface........................................................................................................................................... 26 supervision ........................................................................................................................................................... 26 off-hook detection ............................................................................................................................................... 26 ring trip ................................................................................................................................................................ 26 thermal shutdown................................................................................................................................................ 27 relay driver .......................................................................................................................................................... 27 solid-state ringing access................................................................................................................................... 27 battery supplies.................................................................................................................................................... 27 dc characteristics .................................................................................................................................................... 27 v-i characteristics................................................................................................................................................. 27 loop length .......................................................................................................................................................... 28 ac design................................................................................................................................................................. 28 codec features and selection summary ............................................................................................................. 28 design equations.................................................................................................................................................. 29 application diagram ................................................................................................................................................ 33 outline diagram....................................................................................................................................................... 34 44-pin plcc ......................................................................................................................................................... 34 ordering information................................................................................................................................................ 35
lucent technologies inc. 3 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring table of contents (continued) tables page table 1. pin descriptions ........................................................................................................................................... 5 table 2. operating conditions and powering ............................................................................................................ 7 table 3. ring trip detector ........................................................................................................................................ 8 table 4. battery feed ................................................................................................................................................ 8 table 5. electrical characteristics of pins pt, pr, and v bf ....................................................................................... 9 table 6. loss of power supplies.............................................................................................................................. 10 table 7. analog signal pins..................................................................................................................................... 11 table 8. ac transmission characteristics................................................................................................................. 13 table 9. logic inputs (ce, cs, and b0?3) and output nstat ............................................................................ 14 table 10. timing requirements (b0?3 and cs) .................................................................................................. 14 table 11. relay driver (rdo) .................................................................................................................................. 14 table 12. battery switch (sw1) and ring break switch (sw2) .............................................................................. 15 table 13. ringing access switch (sw3) ................................................................................................................. 15 table 14. input state coding ................................................................................................................................... 16 table 15. external components required............................................................................................................... 20 table 16. mmc a31a8574aa and mmc a11a8574aa module.............................................................................. 23 figures page figure 1. architectural diagram................................................................................................................................. 4 figure 2. pin layout .................................................................................................................................................. 4 figure 3. switch on-state v-i characteristics sw1 and sw2................................................................................. 16 figure 4. switch on-state v-i characteristics sw3................................................................................................. 16 figure 5. external components required ............................................................................................................... 19 figure 6. resistor network...................................................................................................................................... 23 figure 7. l8574 slic matching requirements ....................................................................................................... 24 figure 8. implementing the noise cancellation function........................................................................................ 25 figure 9. ring trip threshold .................................................................................................................................. 26 figure 10. loop current vs. loop voltage ............................................................................................................... 28 figure 11. equivalent complex terminations .......................................................................................................... 29 figure 12. initial ac interface for complex termination between l8574 slic and t7504 codec .......................... 30 figure 13. revised ac interface c t and c r combined into a single capacitor c s ................................................. 31 figure 14. addition of resistor r sc from xmt to irp ............................................................................................. 31 figure 15. tr-57 application diagram .................................................................................................................... 33
4 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring architectural diagram 12-3330.a (c)r2 figure 1. architectural diagram pin information 12-3383.a (f) figure 2. pin layout +5 a v bat1 tip current driver + ax v xmt relay driver rdo v cca agnd +5 a +5 d dgnd v dd ce cs b0 b1 b2 b3 data interface, latches, and logic 2 nlc switch control nrt receive interface & battery noise cancellation +5 a v bat1 ring current driver protect sw2 50 w protect fgnd v bf v bat1 v bat1 current limiter v bat2 clim switchhook detector v xmt nlc nrt ring trip detector sw1 50 w rts rsw sw3 gto v rng cbn rgbn rcvn ircv nstat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 l8574 xmt ts rs rcvn ircv v cca cbn rgbn agnd pra nc prb n s tat cs nc b2 b1 b0 ce v dd dgnd rdo rts rsw v rng v bat1 nc v bf fgnd nc pr pt nc clim v bat2 agnd v cca nc pta nc nc b3 v bat1 nc
lucent technologies inc. 5 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring pin information (continued) table 1. pin descriptions pin symbol type name/function 1 ircv i receive signal input (+). the differential current ?wing from pt to pr is 200 times the current ?wing into ircv. 2v cca +5 v analog dc supply. +5 v supply for analog circuitry. 3 cbn i battery noise capacitor. the current ?wing out of pr is ?00 times the voltage applied to cbn divided by the impedance connected between rgbn and agnd. connect a capacitor from cbn to v bf to eliminate battery noise from the tip/ring. 4 rgbn i battery noise gain resistor. the current ?wing out of pr is 100 times the cur- rent ?wing into rgbn. connect a resistor from rgbn to agnd to set the gain of the battery noise cancellation circuit. 5 agnd analog ground. ground return for analog circuitry. 7 pra protected ring a. connect to prb via an external coupling network. 8 prb protected ring b. connect to pra via an external coupling network. 9 n s tat o not status. when low, this logic output indicates either a ring trip or an off-hook condition, depending on the input state of the slic. 11 cs i channel select. a low-to-high transition on this logic input stores the data on pins b0?3 into the input latches on the slic. 12 b3 i bit 3. b0?3 determine the state of the slic. see the operating states section. 13 b2 i bit 2. b0?3 determine the state of the slic. see the operating states section. 14 b1 i bit 1. b0?3 determine the state of the slic. see the operating states section. 15 b0 i bit 0. b0?3 determine the state of the slic. see the operating states section. 16 ce i channel enable. a low on this logic input resets latches b0?3 to the 1111 state and disables the channel select input cs. a high on this logic input enables the channel select input cs. 17 v dd +5 v digital dc supply. +5 v supply for logic and switch circuitry. 18 dgnd digital ground. ground return for v dd and the relay driver. 19 rdo o relay driver. this output drives an external relay. 20 rts i ring trip sense. sense input for the ring trip detector. 21 rsw o ringing access switch. ringing relay connects this pin to pin v rng (ringing sup- ply). connect this pin to pin v bf through a 600 w current-limiting resistor. 22 v rng ringing supply voltage. connect this pin to the ringing supply. 23 v bat1 of?e battery supply. negative high-voltage power supply. 25 v bf feed resistor battery supply. negative battery and ringing supply for the loop. connect this pin to the ring of the loop through a 200 w battery feed resistor. 27 fgnd fault ground. 30 pr i/o protected ring. the input to the ring fault protection and output of ring current drive ampli?r (via the ring access switch). connect this pin to the ring of the loop through a 1 k w overvoltage protection resistor. 31 pt i/o protected tip. the input to the tip fault protection and output of tip current drive ampli?r. connect this pin to the tip of the loop through a 1 k w overvoltage protec- tion resistor. connect to pta via an external coupling network.
6 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring pin information (continued) table 1. pin descriptions (continued) on the printed-wiring board (pwb), make the leads to fgnd and v bf as wide as possible for thermal and electrical reasons. also, maximize the amount of pwb copper on all leads connected to this device for the lowest operating temperature. absolute maximum ratings (@ t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those indicated in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. notes: analog voltages (v cca , v bat1 , and v bat2 ) are referenced to agnd, and digital (logic) voltages (v dd ) are referenced to dgnd. the ic can be damaged unless all ground connections are applied before, and removed after, all other connections. furthermore, when power- ing the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. for example, inductance in a supply lead could resonate with the supply ?ter capacitor to cause a destructive overvoltage. pin symbol type name/function 33 clim i current limiter capacitor. connect a 0.1 m f capacitor from this pin to pin v bf . 34 v bat2 of?e battery supply. negative high-voltage power supply. 35 agnd analog ground. ground return for analog circuitry. 36 v cca +5 v analog dc supply. +5 v supply for analog circuitry. 38 pta protected tip a. connect to pt via an external coupling network. 40 v bat1 of?e battery supply. negative high-voltage power supply. 41 xmt o transmit signal output. transmit ampli?r output to codec. 42 ts i tip sense. negative (? input of transmit op amp. connect one high-value resis- tor between ts and the tip of the loop and another high-value resistor between ts and xmt. 43 rs i ring sense. positive (+) input of the transmit op amp. connect one high-value resistor between rs and the ring of the loop and another high-value resistor between rs and agnd (see the application diagram, figure 5). 44 rcvn i receive signal input (?. the differential current ?wing from pt to pr is ?00 times the voltage applied to rcvn divided by the impedance connected between ircv and agnd. parameter symbol min typ max unit +5 v dc supplies (v cca & v dd ) ?.5 7.0 v of?e battery supply v bat1 v bat2 ?3 ?3 0.5 0.5 v v logic input voltage ?.5 v dd + 0.5 v logic input clamp diode current, per pin 20 ma logic output voltage ?.5 v dd + 0.5 v logic output current, per pin (excluding relay driver) 35 ma operating temperature range ?0 125 c storage temperature range t stg ?0 125 c relative humidity range 5 95 % ground potential difference (dgnd to agnd) 3 v
lucent technologies inc. 7 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics in general, minimum and maximum values are testing requirements. however, some parameters may not be tested in production because they are guaranteed by design and device characterization. typical values re?ct the design center or nominal value of the parameter; they are for information only and are not a requirement. mini- mum and maximum values apply across the entire temperature range (?0 c to +85 c) and entire battery range (?5 v to ?0 v). unless otherwise speci?d, typical is de?ed as 25 c, v cca and v dd = +5.0 v, v bat1 and v bat2 = ?8 v. positive currents ?w into the device. table 2. operating conditions and powering 1. not to exceed 26 grams of water per kilogram of dry air. 2. includes current in all external resistors per figure 15. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. v bat1 and v bat2 power supply rejection depends on the battery noise cancellation circuit. the performance stated here applies to v bat2 only during the talk state and v bat1 only during the on-hook transmission state and assumes proper battery noise cancellation (see figure 5). parameter min typ max unit temperature range ?0 85 c humidity range 5 95 1 %rh supply voltages: v cca v dd v bat1 v bat2 v cca ?v dd 4.6 4.6 ?2.5 ?0 5.0 5.0 ?8 ?8 5.5 5.5 ?0 v bat1 0.5 v v v v v supply currents (scan state; no loop current) 2 : i vcca + i vdd (+5 v) i vbat1 (?8 v) + i vbat2 (?8 v) 3.0 ?25 ma m a supply currents (talk or on-hook transmission state; no loop current) 2 : i vcca + i vdd (+5 v) i vbat1 (?8 v) + i vbat2 (?8 v) 6.0 ?.5 ma ma total power dissipation (no loop current) 2 (v cca and v dd = +5 v; v bat1 and v bat2 = ?8 v): talk or on-hook transmission state scan state 240 55 mw mw power supply rejection (tip/ring) 3 : v cca (500 hz? khz; 50 mvrms ripple) v dd (500 hz? khz; 50 mvrms ripple) v bat2 and v bat1 (500 hz? khz; 50 mvrms ripple) 4 v bat2 and v bat1 (2 khz? khz; 50 mvrms ripple) 4 40 50 40 35 50 40 db db db db thermal 3 : thermal resistance (still air) operating t jc thermal shutdown temperature 145 60 135 c/w c c
8 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) ring trip detector table 3. ring trip detector 1. the ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is battery ground. 2. pretrip: ringing must not be tripped by a 10 k w resistor in parallel with an 8 m f capacitor applied across tip and ring. battery feed table 4. battery feed 1. assumes 2 x 200 w external dc feed resistors. 2. when the current-limit circuit is active and the battery switch is off, the longitudinal current must be less than the dc loop current to ensure proper ac transmission. 3. assumes c lim = 33 nf; c lim determines the ac output impedance of the current-limit circuit when it is active. 4. detector values are independent of of?e battery and are valid over the entire range of v bat1 and v bat2 . however, nstat must indicate an on-hook (nstat = 1) if either v bat1 or v bat2 is disconnected (open circuit) from its dc source and an off-hook (nstat = 0) if the l8574 is in thermal shutdown. the status of the thermal shutdown circuit is output on b3 when cs is high (thermal shutdown is a logic 0). v bat1 and v bat2 are de?ed as disconnected depending on the voltage at the power supply pins as follows (the pins of supplies that have more than one pin are shorted together): ?if v bat1 ?0 v (i.e., more negative than ?0 v) and v bat2 ?0 v, then nstat must operate normally. ?if v bat1 3 ?0 v (i.e., more positive than ?0 v) or v bat2 3 ?0 v, then nstat must be on-hook (nstat = 1). 5. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. 6. assumes the external dc feed resistors are matched to 0.2% and proper battery noise cancellation; i.e., a 0.22 m f capacitor from v bf to cbn (see figure 5). 7. assumes proper battery noise cancellation; i.e., a 0.22 m f capacitor from v bf to cbn (see figure 5). parameter min typ max unit ringing source 1 : frequency (f) dc voltage ac voltage 17 ?6 60 20 28 ?7 105 hz v vrms ring trip 2 (nstat = 0): loop resistance trip time (f = 20 hz) nstat valid 1840 200 80 w ms ms parameter min typ max unit loop resistance range 1 (3.17 dbm overload into 600 w ): i loop = 18 ma at v bat2 = ?2 v 1840 w longitudinal current capability per wire 2 8.5 marms dc loop current limit (r loop = 200 w ) 26.5 28 29.5 ma current-limiter ac output impedance 3 : 200 hz to 4 khz 25 w current-limiter transient current (in response to a step voltage change on v bf ) 8 150 ma switchhook detector loop resistance 4 : off-hook (nstat = 0) on-hook (nstat = 1) 4400 3300 2700 w w w longitudinal to metallic balance ieee 5 std. 455 6 : 200 hz to 1 khz 1 khz to 3 khz 58 53 db db metallic to longitudinal (harm) balance 7 : 200 hz to 4 khz 30 db
lucent technologies inc. 9 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) fault protection pins pt, pr, and v bf pins pt, pr, and v bf are protected by scrs which clamp surge currents (both positive and negative) to fgnd. if the scr on pr or v bf triggers due to a negative surge, the l8574 automatically switches to the disconnect state while the scr is conducting current above its hold current. after the scr releases, the l8574 automatically switches back to the operating state prior to the scr trigger. table 5. electrical characteristics of pins pt, pr, and v bf 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. applied voltage is 50 vpp square wave at 100 hz to measure dv/dt sensitivity. parameter min typ max unit pt and pr: surge current 1 : lightning?0 m s x 1000 m s lightning? m s x 10 m s power cross?0 hz, 50 ms power cross?0 hz, 1 s power cross?0 hz, 15 min. 1 2.5 600 200 50 a a marms marms marms scr trigger voltage pin pt: positive negative dc transient response v cca ?2 ?5 ?5 v cca + 4 ?5 ?5 v v v scr trigger voltage pin pr: positive negative 150 ?20 280 320 v v scr hold current (positive and negative) 10 ma v bf : surge current 1 : lightning?0 m s x 1000 m s lightning? m s x 10 m s power cross?0 hz, 50 ms power cross?0 hz, 1 s power cross?0 hz, 15 min. 5.5 13 3 800 150 a a arms marms marms scr trigger voltage: positive negative 150 ?20 280 ?20 v v scr hold current (positive and negative) 10 ma trigger current (if from a power supply?t, pr, and v bf ) 250 m a dv/dt sensitivity 1, 2 (pt, pr, and v bf ) 500 v/ m s
10 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) fault protection (continued) loss of power supplies the l8574 must protect itself from lightning and power cross voltages on tip and ring if any (or any combination) of the power supplies (v cca , v dd , v bat1 , and v bat2 ) are disconnected (open circuit) from their dc source. addition- ally, if any power supply is disconnected, no overvoltage on tip or ring can cause a supply voltage to exceed its maximum rating. under these conditions, v cca and v dd are considered as one supply (v cca shorted to v dd ), the pins of supplies which have more than one pin are shorted together, and bypass capacitors are connected. to sat- isfy these requirements (and also to disconnect ringing from the loop when ring trip cannot be detected), the l8574 is placed into the disconnect state depending on the voltage at the power supply pins as shown in table 6. table 6. loss of power supplies parameter min typ max unit v cca and v dd : normal operating state (as de?ed by control logic) disconnect state 1 4.5 v v v bat1 : normal operating state (as de?ed by control logic) disconnect state disconnect state ?0 ?5 ?5 ?0 v v v
lucent technologies inc. 11 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) fault protection (continued) loss of power supplies (continued) table 7. analog signal pins 1. connected per figure 5. 2. a battery or ground short on pt, pr, or xmt shall not cause a device failure. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter min typ max unit pt and pr: surge current (see the protection section.) output drive (pt): drive current negative voltage swing (i out + 10 ma) positive voltage swing (i out ?10 ma) dc bias current 15 v bat1 + 4.5 v cca ?3.5 600 v bat1 v cca 900 ma v v m a output drive (pr): positive (sink) drive current negative voltage swing (i out + 10 ma) positive voltage swing (i out ?10 ma) dc bias current (v bat2 = v bat1 ?48 v) 1 15 v bat1 + 4.5 v cca ?3.5 ?.8 v bat1 v cca ?.4 ma v v ma output short-circuit transient current 2 output impedance (60 hz?.4 khz) 3 output load resistance (dc or ac) 3 output load capacitance 3 250 100 125 1 ma k w w nf xmt: output drive current output voltage swing (1 ma load): maximum minimum output short-circuit dc current output impedance (60 hz?.4 khz) 3 output load dc resistance 3 output load ac resistance output load capacitance 3 1 v bat1 v bat1 + 5 50 2 v cca 2.5 20 10 50 ma v v ma w k w k w pf
12 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) fault protection (continued) loss of power supplies (continued) table 7. analog signal pins (continued) 1. connected per figure 5. 2. a battery or ground short on pt, pr, or xmt shall not cause a device failure. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter min typ max unit rcvn: input voltage range input bias current input impedance 3 ?.75 20 v cca ?1.0 1 v m a m w ircv: input offset voltage (to rcvn) input impedance 3 20 5 mv w cbn: surge current (lightning 10 m s x 1000 m s) input voltage range input bias current input impedance 3 input positive clamp voltage (i cbn = +100 m a) input negative clamp voltage (i cbn = ?00 m a) ?.75 50 1.50 ?.00 100 1.25 250 1.90 ?.20 ma v na m w v v rgbn: input offset voltage (to cbn) input impedance 3 10 5 mv w ts and rs: surge current from external source input voltage range 3 input bias current differential input impedance 3 common-mode input impedance 3 external capacitance (67 k w source impedance) 3 v bat1 + 3 50 50 25 agnd 1 10 madc v m a k w m w pf
lucent technologies inc. 13 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) transmission characteristics transmit direction is tip/ring to xmt. receive direction is ircv/rcvn to tip/ring. table 8. ac transmission characteristics 1. requires external components connected as shown in figure 5. transmission characteristics are speci?d assuming a 900 w resistive ter- mination and 1% external resistors. 2. transmission characteristics are speci?d assuming a 900 w resistive termination; however, feedback using external components allows the user to adjust the termination impedance from 900 w to most itu-t recommended complex termination impedances. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter 1 min typ max unit ac termination impedance 2 600 w return loss 3 : 200 hz?00 hz 500 hz?500 hz 2500 hz?400 hz 21 26 21 db db db tip/ring signal level (600 w reference) 3.14 dbm total harmonic distortion (200 hz? khz) 3 0.3 % transmit gain (f = 1 khz): (tip/ring) to xmt ?.486 ?.500 ?.514 receive gain (f = 1 khz): ircv to differential current flowing from ipt to ipr rcvn to ircv 195 0.995 200 1 205 1.005 gain vs. frequency (transmit and receive; 1 khz reference) 3 : 200 hz?00 hz 300 hz?.4 khz 3.4 khz?0 khz 20 khz?66 khz ?.00 ?.30 ?.0 0 0 0 0.05 0.05 1.0 1.0 db db db db gain vs. level (transmit and receive; 0 dbv reference) 3 : ?0 db to +3 db ?.05 0 0.05 db transhybrid loss 3 : 200 hz?00 hz 500 hz?500 hz 2500 hz?400 hz 21 26 21 db db db idle-channel noise (tip/ring): psophometric 3 c-message 3 khz flat 3 ?7 12 20 dbmp dbrnc dbrn idle-channel noise (xmt): psophometric 3 c-message 3 khz flat 3 ?7 12 20 dbmp0 dbrnc0 dbrn0
14 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) data interface and logic table 9. logic inputs (ce, cs, and b0?3) and output nstat 1. unless otherwise speci?d, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. table 10. timing requirements (b0?3 and cs) a low-to-high transition on pin cs latches the data on pins b0?3 into the device. when cs is either high or low, the device is unaffected by data on pins b0?3. the status of the thermal shutdown circuit is output on b3 when cs is high (thermal shutdown is a logic 0). a low on channel enable lead ce asynchronously resets the data latch to 1111 (scan state with the relay driver off) and disables cs so that cs cannot latch any data into the device. a high on ce enables cs. 1. unless otherwise speci?d, all times are measured from the 50% point of logic transitions. 2. these parameters are not tested in production. they are guaranteed by design and device characterization. table 11. relay driver (rdo) the relay driver output rdo is low (relay operated) when a low input on b3 is latched into the device. 1. unless otherwise speci?d, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter 1 symbol min max unit high-level input voltage v ih 2v dd v low-level input voltage v il 0 0.8 v input bias current (high and low) i in 10 m a high-level output voltage (i out = ?00 m a) v oh v dd ?1.5 v dd v low-level output voltage (i out = 180 m a) v ol 0 0.4 v output short-circuit current (v out = v dd )i oss 135ma output load capacitance 2 c ol 050pf parameter 1, 2 symbol min max unit cs rise and fall time (10% to 90%) t r , t f 050ns maximum input capacitance c in ?pf minimum setup time from b0?3 valid to cs t sds 150 ns minimum hold time from cs to b0?3 not valid t hds 50 ns minimum pulse width of cs t wcs 225 ns parameter 1 symbol min max unit off-state output current (v rdo = v dd )i off 10 m a on-state output voltage (i rdo = 70 ma) v on 0 1.0 v on-state output voltage (i rdo = 20 ma) v on 0 0.40 v clamp diode reverse current (v rdo = 0) i r 10 m a clamp diode on voltage (i rdo = 150 ma) v oc v dd v dd + 2.0 v turn-on time 2 t on ?0 m s turn-off time 2 t off ?0 m s
lucent technologies inc. 15 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) switch characteristics table 12. battery switch (sw1) and ring break switch (sw2) 1. sw2 must be off if the voltage on pin pr is more positive than v cca . 2. at 25 c. maximum voltage rating has a temperature coef?ient of +0.167 v/ c. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. applied voltage is 100 vpp square wave at 100 hz to measure dv/dt sensitivity. table 13. ringing access switch (sw3) 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. applied voltage is 100 vpp square wave at 100 hz to measure dv/dt sensitivity. parameter min typ max unit off-state 1 : maximum differential voltage dc leakage current (v sw 320 v) feedthrough capacitance 3 320 2 50 50 v m a pf on-state (see figures 3 and 4.): resistance (r on ) maximum differential voltage (v max ) current limit (i limit ) 20 50 35 100 320 2 60 w v ma dv/dt sensitivity 3, 4 200 v/ m s parameter min typ max unit off-state: maximum differential voltage dc leakage current (v sw = 500 v) dc leakage current (v sw = 250 v) feedthrough capacitance 1 500 20 1 10 v m a m a pf on-state (see figures 3 and 4.): crossover offset voltage (v os ; i sw = 1 ma) resistance (r on ) surge current (10 m s x 1000 m s pulse) 1 release current 1 0.1 3 10 2.0 3 v w a ma dv/dt sensitivity 1, 2 500 v/ m s
16 16 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring electrical characteristics (continued) switch characteristics (continued) 12-3332 (f) figure 3. switch on-state v-i characteristics sw1 and sw2 12-3333 (f) figure 4. switch on-state v-i characteristics sw3 operating states the l8574 has eight operating states. these states are selected using three logic input bits, b0?2, according to the truth table shown in table 14. logic input b3 operates a relay driver independent of the state of bits b0?2. data on the parallel data bus, b0?3, is loaded into a 4-bit latch on the l8574 on the low-to- high transition of the channel select lead cs. changes in the data at inputs b0?3 do not affect the l8574 while cs is either low or high. a low on channel enable lead ce asynchronously resets the 4-bit latch to 1111 (scan state with the relay driver off) and disables the channel select lead cs (i.e., cs is prevented from load- ing any data into the 4-bit latch). a high on ce enables cs. state transitions and delays between transitions are left to the discretion of the user since, except for fault conditions described later, the state of the l8574 depends only on the external control provided through the logic interface. table 14. input state coding scan state n normal on-hook supervision state. n the receive transmission path is powered down; the transmit path is powered up. n the battery feed is connected to the high battery supply (v bat1 ). n the current limiter is powered down and disabled. n sw1 is closed; sw2 and sw3 are open. n nstat re?cts the status of the switchhook detector. +i limit i sw +1.5 v 2/3 r on r on ?.5 v 2/3 r on ? limit ? max current limiting +v max v sw current limiting i sw v sw r on ? os +v os r on ce b3 b2 b1 b0 state 0xxxx scan state with relay driver off 1 x 1 1 1 scan 1 x 1 1 0 disconnect 1 x 1 0 1 alternative talk?w1 closed 1 x 1 0 0 talk?w1 open 1 x 0 1 1 scan current limit 1 x 0 1 0 ringing 1 x 0 0 1 on-hook transmission 1 x 0 0 0 intermediate talk 1 0 x x x relay driver output (rdo) is low (relay active) 1 1 x x x relay driver output (rdo) is high (relay not active)
lucent technologies inc. 17 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring operating states (continued) disconnect state n forward disconnect state. n the receive transmission path is powered down; the transmit path is powered up. n the current limiter is powered down and disabled. n sw1, sw2, and sw3 are open. n pins pt, pr, and v bf are high impedance (>100 k w ). n nstat is forced high (on-hook). alternate talk state n alternate talk state. n the battery feed is connected to the high battery supply (v bat1 ). n the receive and transmit transmission paths are both powered up. n the current limiter is powered up and active. n sw1 and sw2 are closed; sw3 is open. n nstat re?cts the status of the switchhook detector. talk state n normal talk state. n the battery feed is connected to the high battery supply (v bat2 ). n the receive and transmit transmission paths are both powered up. n the current limiter is powered up and active. n sw2 is closed; sw1 and sw3 are open. n nstat re?cts the status of the switchhook detector. scan current-limit state n alternate on-hook supervision state. n same as scan state but with the current limiter pow- ered up and active. n the receive transmission path is powered down; the transmit path is powered up. n sw1 is closed; sw2 and sw3 are open. n nstat re?cts the status of the switchhook detector. ringing state n normal ringing state. n the receive and transmit transmission paths are both powered down. n sw3 is closed; sw1 and sw2 are open. n the current limiter is powered down and disabled. n nstat re?cts the status of the ring trip detector. on-hook transmission state n normal on-hook transmission state. n the battery feed is connected to the high battery supply (v bat1 ). n the receive and transmit transmission paths are both powered up. n the current limiter is powered down and disabled. n a 10 ma dc bias current ?ws out of the ring current driver into pr, and a 5 ma dc bias current ?ws into the tip current driver from pt (the switchhook detec- tor is adjusted to compensate for this dc bias cur- rent). n sw1 and sw2 are closed; sw3 is open. n nstat re?cts the status of the switchhook detector.
18 18 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring operating states (continued) intermediate talk state n talk state with an increased and current-limited out- put impedance. n same as talk state. n the current limiter is powered up and active, but the output capacitance at v bf is reduced to approxi- mately 350 times i lim . this allows rapid settling of the v bf voltage during transitions from on-hook transmis- sion to the talk state. n a 10 ma dc bias current ?ws out of the ring current driver into pr, and a 5 ma dc bias current ?ws into the tip current driver from pt (the switchhook detec- tor and current limiter are adjusted to compensate for this dc bias current). n sw2 is closed; sw1 and sw3 are open. n nstat re?cts the status of the switchhook detector. applications general the l8574 supplies a precise differential current to the tip/ring pair (via pt and pr) as a function of analog signals on ircv and rcvn. however, the current driv- ers connected to pt and pr are not designed to supply dc feed current to the loop. the dc loop current is fed by two external 200 w resistors. when a loop is idle (on- hook), the battery switch (sw1) is turned on to connect the ring lead to v bat1 which is typically ?8 v, thus pro- viding suf?ient tip/ring open circuit voltage to operate various types of customer premises equipment (cpe). transmission may or may not be enabled in the idle dc feed condition. if transmission is enabled (on-hook transmission), the current drivers are biased so that they can both source and sink suf?ient signal current when no dc loop current is ?wing (even in the pres- ence of longitudinal currents on tip and ring). when the loop is off-hook, the battery switch (sw1) is turned off and the current limiter becomes active. this con- nects the ring lead to v bat2 (typically ?8 v) through an accurate current limiter circuit which saves off-hook power dissipation. to ensure proper ac performance, the ac output impedance of the current limiter must be small. the effective output capacitance at v bf is approximately 7500 times c lim when the current limiter is active. the external 200 w dc feed resistors will, for the most part, determine the longitudinal balance of the slic; thus, they must be matched appropriately to meet the longitudinal balance requirements (0.2% for 58 db bal- ance, 0.35% for 52 db balance). the impedance of the battery switch and current limiter in series with the ring- side dc feed resistor is reduced by the battery noise cancellation circuit so that it has minimal effect on the longitudinal balance. the dc feed resistors also have a signi?ant impact on the termination impedance of the slic. feedback, using external components, allows the user to adjust the termination impedance from the 400 w dc feed resistance to satisfy most resistive and complex termination impedances. because the l8574 does not supply dc feed current to the loop outputs, pt and pr can be coupled to the tip and ring through a suf?iently high resistance to allow for simple lightning protection of the drivers. however, the resistance must be low enough to achieve the coupling of suf?ient ac signal to the tip and ring from the available power supply. since the tip and ring drivers are current sources, the value of this resistance does not affect the performance of the slic and is somewhat arbitrary. the value chosen is typically 1000 w . the l8574 also senses the differential tip/ring voltage via sense inputs ts and rs. the differential dc voltage is used internally for switchhook detection. the detec- tor threshold is preset internally. the differential tip/ ring ac signal appears on analog output xmt. also included on the l8574 are scr protectors, a relay driver, one logic output (indicates switchhook and ring trip status), a 4-bit parallel logic interface, a ringing access switch, a ring trip detector, and a circuit which eliminates the battery noise that is coupled to the tip and ring through the dc feed resistors. the following diagram and table show the basic com- ponents required with the l8574 slic. speci? compo- nent values are given in cases where the value is ?ed. in cases where the value may change (i.e., compo- nents that determine the ac interface), the value is not listed but equations to determine these values are given later in this document.
lucent technologies inc. 19 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) general (continued) 12-3384.d (f) * optional components to improve psrr by 6 db. figure 5. external components required r1 r2 pta prb pra v rng v bat2 fgnd v bat1 r3 100 k w r5 200 k w +5 d v cca agnd v dd dgnd +5 d 0.1 m f cv dd l8574 rcvn xmt pt ts pr r10 600 k w rs v bf rsw c lim 33 nf rts 0.22 m f c rt 0.1 m f cbn clim vf r o(n) b3 b0 b2 ce b1 parallel data interface to control logic cs n s tat ircv rgbn rdo 19 16 15 14 13 12 11 9 44 1 4 gs x (n) 1/4 t7504 vf x in(n) r rv1 r hb1 k1 17 18 2, 36 2, 27, 35 ringing supply 19.6 k w c bias1 20 v 27 23, 34 22 7 8 38 40 r bias2 c bias2 + v fx c b1 r4 r6 200 k w r8 1 k w r7 1 k w r rt 1 m w 41 42 31 30 43 25 21 20 33 3 r cbn3 r cbn2 1 m w 5.11 k w dg 0.1 m f 200 w 100 k w 200 w r cbn1 c cbn1 r cbn4 301 k w 9.53 k w c cbn2 0.01 m f r bias1 10 m f d speed 0.47 m f 19.6 k w c vbat 0.1 m f resistor module r9 20 k w r rv2 r gx c b2 0.1 m f r t1 v fx xmt c 2 r t2 0.1 m f cv cc resistor module r cx1 r gbn c gbn 50 k w * 47 pf* tip ring f1 f2
20 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) general (continued) table 15. external components required 1. power is continuous rms power. 2. r 1 /r 2 = 1, with a tolerance of 0.35% for 50 db longitudinal balance, 0.2% for 58 db longitudinal balance. fuses f1 and f2 provide fail-safe operation if excessive overvoltage conditions exist on tip and ring. they will not operate if the total power dissipation of the entire resistor network is 5 w at 85 c. 3. (r 3 + r 6 )/(r 4 + r 5 ) = 1 with a tolerance of 0. 35% for 50 db longitudinal balance, 0.2% for 58 db longitudinal balance. 4. r 9 /r 1 = 100 with a tolerance of 0.5%. comp. function implementation value attribute 1 f1 fuse protector resistor module f2 fuse protector resistor module r 1 dc feed protection resistor module 200 w 1.0%, 2 w 2 r 2 dc feed protection resistor module 200 w 1.0%, 2 w 2 r 3 transmit gain resistor module 100 k w 1.0%, 25 mw 3 r 4 transmit gain resistor module 100 k w 1.0%, 25 mw 3 r 5 transmit gain resistor module 200 k w 1.0%, 25 mw 3 r 6 transmit gain resistor module 200 k w 1.0%, 25 mw 3 r 7 protection resistor module 1 k w 2.0%, 0.1 w r 8 protection resistor module 1 k w 2.0%, 0.1 w r 9 battery noise cancellation resistor module 20 k w 10 mw 4 r 10 ringing resistor module 600 w 1.0%, 1.6 w (14 w for 250 ms) c vcc v cc filter external 0.1 m f 20%, 10 v c vdd v dd filter external 0.1 m f 20%, 10 v c bat v bat filter external 0.1 m f 20%, 100 v c lim current limit external 33 nf 20% 100 v r cbn1 battery noise cancellation external 5.11 k w 1%, 1/16 w r cbn2 battery noise cancellation external 301 k w 1%, 1/16 w r cbn3 battery noise cancellation external 9.53 k w 1%, 1/16 w r cbn4 battery noise cancellation external 1 m w 1%, 1/16 w c cbn1 battery noise cancellation external 0.22 m f 20%, 100 v
lucent technologies inc. 21 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) general (continued) table 15. external components required (continued) 1. power is continuous rms power. 2. r 1 /r 2 = 1, with a tolerance of 0.35% for 50 db longitudinal balance, 0.2% for 58 db longitudinal balance. fuses f1 and f2 provide fail-safe operation if excessive overvoltage conditions exist on tip and ring. they will not operate if the total power dissipation of the entire resistor network is 5 w at 85 c. 3. (r 3 + r 6 )/(r 4 + r 5 ) = 1 with a tolerance of 0. 35% for 50 db longitudinal balance, 0.2% for 58 db longitudinal balance. 4. r 9 /r 1 = 100 with a tolerance of 0.5%. 5. optional components to improve psrr by 6 db. comp. function implementation value attribute 1 c cbn2 battery noise cancellation external 0.01 m f 20%, 100 v c gbn 5 battery noise cancellation external 47 pf 20%, 100 v r gbn 5 battery noise cancellation external 50 k w 20%, 100 v c rt ring trip external 0.1 m f 20%, 100 v r rt ring trip external 1 m w 1%, 1/16 w r bias1 dc bias for on-hook trans. external 19.6 k w 1%, 1/16 w r bias2 dc bias for on-hook trans. external 19.6 k w 1%, 1/16 w c bias1 ac transmission external 10 m f 20%, 100 v c bias2 ac transmission external 0.47 m f 20%, 100 v d speed reduce settling time off-hook to on-hook external 20 v zener c b1 dc blocking external 0.1 m f 20%, 10 v c b2 dc blocking external 0.1 m f 20%, 10 v r t1 ac interface external see ac design equations 1%, 1/32 w r t2 ac interface external see ac design equations 1%, 1/32 w r gx ac interface external see ac design equations 1%, 1/32 w r gx1 ac interface external see ac design equations 1%, 1/32 w r rv1 ac interface external see ac design equations 1%, 1/32 w r rv2 ac interface external see ac design equations 1%, 1/32 w c 2 ac interface external see ac design equations 1%, 1/32 w r hb1 ac interface external see ac design equations 1%, 1/32 w
22 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) resistor module the l8574 requires certain external resistors at the tip and ring interface. because of matching and protection requirements, one of the most economical options recommended to implement these resistors is in a thick-?m resistor module. a schematic and a brief description of the function of each of these resistors is given in figure 6. note that microelectronic modules corporation mmc * a31a8574aa and mmc a11a8574aa thick-?m resistor modules are application-speci? resistor modules designed for use with the l8574 slic. the values, tolerance, matching, and power rating of the mmc a31a8574aa and mmc a11a8574aa modules are given in table 16. resistors r 1 and r 2 are the dc feed resistors. r1 is connected from battery to ring and r 2 is connected from tip to ground. the dc loop current is fed to the subscriber loop via these resistors. the resistors set the dc feed resis- tance, which is r 1 + r 2 (400 = 200 + 200). resistors r 1 and r 2 also provide a common-mode impedance of (200 || 200) 100 w . these resistors will primarily determine the longitudinal balance of the line circuit; thus, they must be matched appropriately to meet longitudinal balance requirements (0.35% for 50 db and 0.2% for 58 db). also, they have a signi?ant impact on the termination impedance of the slic. feedback using external components (external components when a ?st- or second-gener- ation codec is used) allows the user to set the termination impedance at 600 w , or most itu-t recommended ter- mination impedances. under normal operating conditions, the current through resistors r 1 and r 2 is limited by the current-limit circuitry to 25 ma. thus, the 2 w rating of resistors r 1 and r 2 in mmc a31a8574aa and mmc a11a8574aa is adequate for normal operation. the power rating of these resistors is discussed more in the protection section of this data sheet. * mmc is a registered trademark of microelectronic modules corporation. for additional information, contact microelectronic modules corpo- ration (mmc), 2601 s. moorland rd., new berlin, wi 53151 u.s.a.: tel. 414-785-6506, fax 414-785-6516, e-mail sales@mmccorp.com.
lucent technologies inc. 23 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) resistor module (continued) 5-5279 (f) notes: 1. pin numbers and resistor labels are per mmc a31a8574aa and mmc a11a8574aa descriptions. 2. node labels are per l8574 package. 3. for 600 v power cross, resistor networks should ?pen in less than 40 ms. figure 6. resistor network table 16. mmc a31a8574aa and mmc a11a8574aa module 1. continuous (rms) power. 2. for 50 db longitudinal balance; 0.2% for 58 db balance. note: fuses f1 and f2 provide fail-safe operation if excessive overvoltage conditions exist on tip and ring. they will not operate if the total power dissipation of the entire resistor network is 5.0 w @ 85 c. resistor value tolerance power 1 surge rating r 1 200 w 1.0% 2.0 w lightning: power cross r 2 200 w 1.0% 2.0 w lightning: power cross r 3 100 k w 1.0% 25 mw none r 4 100 k w 1.0% 25 mw none r 5 200 k w 1.0% 25 mw lightning: power cross r 6 200 k w 1.0% 25 mw lightning: power cross r 7 1 k w 2.0% 0.1 w lightning: power cross r 8 1 k w 2.0% 0.1 w lightning: power cross r 9 20 k w 10 mw none r 10 600 w 1.0% 1.6 w 14 w for 250 ms r 9 /r 1 100 0.5% r 1 /r 2 1 0.35% 2 (r 3 + r 6 )/(r 4 + r 5 ) 1 0.35% 2 1 ring pr rgbn gnd rs v bf gnd rsw ts xmt pt tip f2 r 7 2345 r 9 r 3 7 6 r 5 r 10 r 6 r 4 12 11 10 9 81314 f1 r 8 r 2 r 1
24 24 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) resistor module (continued) resistors r 3 ? 6 set the gain of the slic in the transmit (2-wire to 4-wire) direction. this is shown in figure 7. 5-5277 (f) figure 7. l8574 slic matching requirements the matching of resistors r 3 ? 6 will determine the gain accuracy of the slic; therefore, these resistors must be matched accordingly. their matching require- ments are given in table 16. because of the high resistance values, the normal operating power of resistors r 3 ? 6 will be relatively low. given design margin and thick-?m technology capabilities, a power rating of 250 mw for these resis- tors is not unreasonable. resistors r 7 and r 8 are used to couple the pt and pr current drive ampli?rs to tip and ring. since pt and pr drive ampli?rs are current sources, the value of the series resistance does not affect the loop length or other performance of the slic, and may be arbitrarily high for protection purposes. a value of 1 k w is ade- quate for protection purposes. under normal operating conditions, these resistors will see the battery voltage less the tip/ring voltage. assuming a tip/ring voltage of 6 v (representative of a short into a handset), the normal continuous operating power of r 7 and r 8 is given by: (48 v ?6 v) e2/2.0 k w = 0.882 w per r 7 and r 8 resis- tor pair 882 mw/2 = 441 mw per resistor (r 7 and r 8 ) hence, the operating power rating of 500 mw for r 7 and r 8 . this is the normal rating for r 7 and r 8 under normal operating conditions. the ability of these resis- tors to withstand fault conditions depends on the power rating. resistor r 9 is also included on the thick-?m resistor module. this resistor is used to set the gain of the bat- tery noise cancellation circuit. see the battery noise cancellation section of this data sheet for design equa- tions to set the value of r 9 . power ringing is applied to the line circuit through resis- tor r 10 . one side of r 10 is connected to l8574 node rsw. rsw is the output of the integrated solid-state ringing access switch, sw3. the other side of r 10 is connected to the 200 w ring feed resistor, r 1 . resistor r 10 also serves as a current-limiting resistor. fault cur- rent through the solid-state ringing access switch, sw3, is limited by r 10 . sw3 is rated for 2 a maximum for a 10 m s x 1000 m s (lightning) pulse. continuous cur- rent through this switch should be less than 150 ma. r 10 in resistor modules mmc a31a8574aa and mmc a11a8574aa is chosen to be 600 w . protection because of the resistive feed architecture, a simple inexpensive protection scheme that does not require an external protection device may be used. the mmc a31a8574 resistor module has speci?ations which are quali?d to itu-t k20, ul * 1459, ul 497a, fcc part 68.302 (d) & (e), and rea form 397g speci?a- tion. the mmc a11a8574aa resistor module, in addi- tion to meeting all the speci?ations of the mmc a31a8574, also meets bellcore 1089 requirements. lightning and power-cross protection are provided by the two external dc feed (and current-limiting) resis- tors, r 1 and r 2 , in the external resistor module. under fault conditions, these resistors serve as fault current- limiting resistors. these resistors are designed to sur- vive lightning surges. they are also designed to contin- uously dissipate 4 w each and to survive 1 arms @ 60 hz power crosses of 1 second in duration. sus- tained power dissipation above these levels will cause degradation and eventual failure; however, the resistors are designed to fail gracefully under these conditions. pins pt and pr are isolated from the loop by external 1000 w resistors, and pin v bf is isolated from the loop by the ring-side, 200 w dc feed resistor. these pins must have adequate fault protection which operates outside of their normal operating voltages. all three pins are protected by scrs which clamp the surge currents (both positive and negative) to fgnd. the tip ring r 5 200 k w r 6 200 k w r 4 100 k w + xmt r 3 100 k w * ul is a registered trademark of underwriters laboratories, inc.
lucent technologies inc. 25 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) protection (continued) sense inputs, ts and rs, are protected with diodes to battery (v bat1 ) and v cca and the series high-value external resistors which connect them to tip and ring. because the battery noise cancellation input cbn is connected to pin v bf through a 0.1 m f capacitor, it must also be protected. internally, it is protected with an 8 v zener diode connected to v cca . an external resistor of at least 3 kw (5 kw is recommended) is required to limit the surge current. no external protection device is required. tip/ring drivers the l8574 has two tip/ring drivers with outputs called pt and pr. each driver operates as a current source capable of sinking or sourcing adequate ac signal cur- rent plus the dc bias current that is required during on- hook transmission. receive interface the receive interface circuitry couples the differential signal on receive inputs ircv and rcvn to the tip/ ring drivers. input ircv is a low-impedance (<5 w ) current input while rcvn is a high-impedance voltage input. internal feedback forces the voltage at ircv to be equal to rcvn so that a voltage applied to rcvn causes a current ?w out of ircv which equals that voltage divided by the impedance connected from ircv to agnd (assuming the input voltage is refer- enced to agnd). the receive interface and tip/ring drivers provide a current gain of 200; i.e., a differential output current ?ws from pt to pr which is 200 times the current ?wing into ircv. the receive interface also provides a level shift since the inputs, ircv and rcvn, are refer- enced to analog ground, while the outputs, pt and pr, swing between v cca and v bat1 . the receive interface ensures that the input current is not converted to a common-mode current at pt and pr. transmit interface the transmit interface circuitry interfaces the differen- tial voltage on tip and ring to transmit output xmt. the tip/ring differential voltage (both ac and dc) appears on output xmt with a gain of 0.5. the transmit interface uses an operational ampli?r with four external resis- tors to perform a differential to single-ended conver- sion. the operational ampli?r inputs are ts and rs. output xmt is referenced to ground (agnd). the lon- gitudinal balance and gain accuracy at xmt depends on the matching of the external resistors (0.35%). because a large dc potential exists at xmt, a capacitor must be used to couple the ac signal to the low-voltage codec circuitry. battery noise cancellation the battery noise cancellation circuit senses the ac noise on the battery via the capacitor connected from input cbn to v bf . it couples this noise, 180 out of phase, to the ring current drive ampli?r. this cancels the battery noise that is coupled to the ring through the feed resistor connected to v bf . additionally, it ensures longitudinal balance, which depends only on the matching of the battery feed resis- tors by creating an ac ground at v bf with respect to sig- nals on the ring lead. for the cancellation to operate properly, both the phase and gain must be accurate. the battery noise cancella- tion gain is a transconductance which is equal to 100 divided by the resistor connected from rgbn to ground (agnd). this value must be equal to the recip- rocal of the dc feed resistor (1/200). that is: 100/r 9 = 1/200 r 9 = 20 k w it is advantageous if resistors r 9 and r 1 are matched and tracked thermally, i.e., located on the same ?m integrated circuit (fic). psrr can be improved by adding a 47 pf capacitor in series with a 50 k w resistor from r gbn to ground. also, to implement the battery noise cancellation func- tion, connect the following circuit from cbn to v bf and analog ground. 5-5278a (f) figure 8. implementing the noise cancellation function v bf cbn 301 k w 0.1 m f 5.11 k w 0.01 m f l8574
26 26 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) on-hook transmission during the on-hook transmission and talk/on-hook transmission states, the l8574 provides 750 m a dc bias current out of the tip/ring current driver ampli?rs. this creates a dc voltage drop across the external 19.6 k w resistors, r bias1 and r bias2 , which provides suf? cient dc bias to support on-hook transmission. the switchhook detector is adjusted to compensate for this dc bias current. the l8574 is able to support on-hook transmission to drive a 3.17 dbm signal into a 600 w or 900 w ac loop. the capacitors, c bias1 and c bias2 , pro- vide an ac path so transmission is not distorted by r bias1 and r bias2 . zener diode, d speed , reduces the settling time transition from on- to off-hook. parallel data interface a 6-wire parallel interface (ce, cs, b0, b1, b2, and b3) is used to pass control information from the control logic on the line card to the l8574. the l8574 has eight operating states. these states are selected using three logic input bits, b0?2, according to the truth table shown in table 14. logic input b3 operates a relay driver independent of the state of bits b0?2. data on the parallel data bus, b0?3, is loaded into a 4-bit latch on the l8574 on the low-to-high transition of the channel select lead cs. changes in the data at inputs b0?3 do not affect the l8574 while cs is either low or high. a low on channel enable lead ce asynchronously resets the 4-bit latch to 1111 (scan state with the relay driver off) and disables the channel select lead cs (i.e., cs is prevented from loading any data into the 4-bit latch). a high on ce enables cs. state transitions and delays between transitions are left to the discretion of the user since, except for fault con- ditions, the state of the l8574 depends only on the external control provided through the logic interface. supervision the l8574 offers the ring trip, loop closure, and ther- mal shutdown functions. the status of these functions are provided as device outputs. the outputs of the ring trip and off-hook supervision detectors are multiplexed into a single output called ns tat. the device state determines which output is connected to ns tat. the device state table, table 14, details which supervision output (loop closure or ring trip) is seen at nstat dur- ing a given device state. detector values are independent of of?e battery and are valid over the entire range of v bat1 and v bat2 . how- ever, nstat must indicate an on-hook (nstat = 1) if either v bat1 or v bat2 is disconnected (open circuit) from its dc source and an off-hook (nstat = 0) if the l8574 is in thermal shutdown. v bat1 and v bat2 are de?ed as disconnected depending on the voltage at the power supply pins as follows (the pins of supplies which have more than one pin are shorted together): if v bat1 ?0 v (i.e., more negative than ?0 v) and v bat2 ?0 v, then nstat must operate normally. if v bat1 3 ?0 v (i.e., more positive than ?0 v) or v bat2 3 ?0 v, then nstat must be on-hook (nstat = 1). the status of the thermal shutdown circuit is output on b3 when cs is high (thermal shutdown = 0 v). off-hook detection the off-hook or loop closure threshold on the l8574 slic is internally ?ed. off-hook is indicated (nstat = 0) if the loop resistance is a maximum 2700 w . on- hook is indicated (nstat = 1) if the loop resistance is a minimum 4400 w . ring trip the ring trip threshold is set by resistor r 10 in the resis- tor module. with r 10 set to 600 w , the circuit is guaran- teed to ring trip up to 1840 w . with a 20 hz ringing source, the trip time is guaranteed less than 200 ms. the ring trip circuit assumes uses of battery-backed ringing. pretrip immunity is such that a load across tip and ring of 10 k w in parallel with an 8 m f capacitor will not cause ring trip. three external components are required for ring trip, a 1 m w resistor from r ts to v bf , resistor r 10 , which is a 600 w resistor from r sw to v bf , and a 0.1 m f capacitor from r sw to r ts . the components required for ring trip circuit are shown in figure 9. note that r 10 is implemented in the resistor module. all other components are discrete. 5-5276 (f) figure 9. ring trip threshold 600 w r 10 1 m w rts rsw v bf 0.1 m f l8574
lucent technologies inc. 27 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring applications (continued) thermal shutdown if the silicon temperature rises above a nominal 145 c, the l8574 will enter a thermal shutdown mode where all switches are off and the slic is in a state that is functionally equivalent to the disconnect state. relay driver the l8574 offers a single integrated relay driver. the relay driver output rdo is low (relay operated) when a low input on b3 is latched into the device. the driver has suf?ient driver capability to provide 70 ma with a 1.0 v drop and 20 ma with a 0.4 v drop. turn-off and turn-on times are a maximum of 10 m s. solid-state ringing access the l8574 offers a solid-state ringing access switch for power ringing access and for the associated line break function. during the ringing state, unbalanced battery- backed power ringing is applied to the ring lead through resistors r 10 and r 1 via ringing access switch sw3. the ring drive ampli?r of the l8574 slic is iso- lated from the subscriber loop via the integrated line break switch sw2 during the power ringing state. since the tip lead of the l8574 slic is tied to ground via resistor r 2 , no line break function is associated with the tip lead. the return ground path for the power ringing signal is via r 2 . the line break switch, sw2, is implemented using a high-voltage mos transistor. this gives a linear v-i characteristic, as seen in figure 3. the on resistance of this switch is a nominal 50 w with a maximum 100 w . this switch is current limited to a nominal 35 ma and has a maximum off-state voltage rating of 320 v. the ringing access switch, sw3, is implemented using a pnpn type structure. this gives a linear v-i characteris- tic with an offset through the origin, as shown in figure 4. this offset is less than 3 v. the off-state voltage rat- ing is 500 v. surge current (10 m s x 1000 m s) through this switch must be limited to less than 2 a. steady state current through this switch must be limited to less than 150 ma. battery supplies there are two battery pins on the l8574, v bat1 and v bat2 . these two nodes may be connected to a com- mon negative battery voltage. the magnitude of the battery should be suf?ient to supply the required dc current into the speci?d (long) loop requirement. integrated into the l8574 is solid-state switch, sw1. sw1 has similar characteristics to the line break switch, sw2, including the 35 ma current limit. when sw1 is closed, the battery is applied through sw1 from the v bat1 node. dc current from the battery will be lim- ited by the current-limiting action of sw1. when sw1 is open, the battery at v bat1 is isolated from the loop. the internal current-limit circuit is associated with the v bat2 node; thus, when the current-limit circuit is active, the battery is applied to the subscriber loop through v bat2 node and through the internal current-limiting circuitry, limiting dc current to the subscriber loop to 28 ma. when the current-limit circuit is not active, the voltage battery at v bat2 is isolated from the loop. the state of sw1 and the current-limiting circuit is con- trolled via logic inputs b0?2. the l8574 state table (table 14) details, for a given operational state, the con- dition of sw1 and the current-limit circuit. dc characteristics v-i characteristics resistors r 1 and r 2 are the dc feed resistors. r 1 is connected from battery to ring, and r 2 is connected from tip to ground. the dc loop current is fed to the subscriber loop via these resistors. when the l8574 is operating in the linear region of the v-i characteristic, the dc feed resistance or slope of this region of opera- tion is determined by the sum of resistors r 1 plus r 2 . the slope of the v-i characteristic will be ?/400 w . when the l8574 is operating in the current-limited region of the v-i characteristic, the current will be con- stant, regardless of loop length, and will be set and ?ed by the internal current-limit circuit. the current limit is internally ?ed to a nominal 28 ma. connect a 33 nf capacitor from c lim to v bf . note that there is a slope of 1/10 k w to the v-i characteristic in the current- limited region of operation.
28 28 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring dc characteristics (continued) v-i characteristics (continued) in longer loops, the l8574 will operate in the linear region of operation, and in short loops, to conserve power, the l8574 will operate in the (?ed) current-limit region of operation. a typical v-i characteristic for the l8574 is shown in figure 10 below. 12-3050.e (c) note: v bat1 = ?8 v, v bat2 = ?8 v; i lim = 28 ma; r dc = 400 w . figure 10. loop current vs. loop voltage loop length the loop range is calculated as follows: r l = ({ | v bat | ?v ohlim }/i limit ) ?r 1 ?r 2 where: r l is the dc resistance of the subscriber loop. v ohlim is the overhead or drop associated with the cur- rent-limit circuit, typically 2.2 v. i limit is the minimum speci?d current that is required at the maximum loop length, typically 18 ma. | v bat | is the minimum magnitude of the battery assume 43.2 v. r 1 = r 2 = dc feed resistors = 200 w . r l = ({43.2 v ?2.2 v}/0.018 a) ?200 w ?200 w = 1877 w . ac design codec features and selection summary there are four key ac design parameters: n termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to mini- mize echo return to the telephone set. n transmit gain is measured from the 2-wire port to the pcm highway. n receive gain is done from the pcm highway to the transmit port. n hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. at this point in the design, the codec needs to be select- ed. the discrete network between the slic and the co- dec can then be designed. below is a brief codec feature and selection summary. first-generation codecs these perform the basic ?tering, a/d (transmit), d/a (receive), and m -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid balance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog out- put stages, and m -law/a-law selectability. this genera- tion of codec has the lowest cost. it is most suitable for applications with ?ed gains, termination impedance, and hybrid balance. second-generation codecs this class of devices includes a microprocessor inter- face for software control of the gains and hybrid bal- ance. the hybrid balance is included in the device. ac programmability adds application flexibility and saves several passive components. it also adds several i/o latches that are needed in the application. it does not have the transmit op amp, since the transmit gain and hybrid balance are set internally. loop current (ma) 01020 50 0 20 30 40 50 loop voltage (v) 30 40 10 1 10 k w i lim ? r dc1 ? 400 =
lucent technologies inc. 29 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring ac design (continued) codec features and selection summary (continued) third-generation codecs this class of devices includes the gains, termination im- pedance, and hybrid balance?ll under microproces- sor control. depending on the device, it may or may not include latches. in the codec selection, increasing software control and ?xibility are traded for device cost. to help decide, it may be useful to consider the following: n will the application require only one value for each gain and impedance? n will the board be used in different countries with dif- ferent requirements? n will several versions of the board be built? if so, will one version of the board be most of the production volume? n does the application need only real termination impedance? n does the hybrid balance need to be adjusted in the ?ld? design equations the following section gives the relevant design equa- tions to choose component values for any desired gain, termination, and balance network, assuming a complex termination is desired. complex termination will be speci?d in one of the two forms shown below. 12-3425(f) figure 11. equivalent complex terminations both forms are equivalent to each other, and it does not matter which form is speci?d. the component values in the interface circuit of figure 11 are calculated assuming the parallel form is speci?d. if the termina- tion impedance to be synthesized is speci?d in the series form, convert it to the parallel form using the equations below: note that if the termination impedance is speci?d as pure resistive: de?e the gain constant, k, as follows: where, r x = desired receive (or pcm to tip/ring) gain in db t x = desired transmit (or tip/ring to pcm) gain in db where |z t | (1 khz) is the magnitude of the complex ter- mination impedance z t being synthesized. this equa- tion assumes that the tlp of the codec is 0 dbm referenced to 600 w . the following equation applies when referring to figure 11: where, w = 2 p| | = 1000 hz cr 1 r 2 is de?ed per figure 11 (series form), and r 1 r 2 c r 2 r 1 c (series form) (parallel form) r 1 r 1 r 2 + = r 2 r 1 2 r 2 r 1 + r 2 ------------------------------ - = c c 12 r 1 r 2 ------ - r 1 r 2 ------ - ? ?? 2 ++ ------------------------------------------ - = r 2 r 2 0 and c = c ~ == = k rcv k 0 10 rx/20 for receive gain = k tx 1 k 0 ------ 10 tx/20 for transmit gain = k 0 z t 1 khz 600 ------------------------- - = = power transfer ratio z t w 2 c 2 r 1 r 2 2 r 1 r 2 j w r 2 2 c ++ 1 w 2 r 2 2 c 2 + -------------------------------------------------------------------------------------- - = z t w 2 c 2 r 1 r 2 2 r 1 r 2 ++ 1 w 2 r 2 2 c 2 + ----------------------------------------------------------- ? ? ?? 2 w r 2 2 c 1 w 2 r 2 2 c 2 + ---------------------------------- - ? ? ?? 2 + =
30 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring ac design (continued) design equations (continued) 12-3429.b (f).r3 figure 12. initial ac interface for complex termination between l8574 slic and t7504 codec note: dc blocking capacitor (c b ) not shown, c t and c r separate v rn receive interface + r t2 r rv2 r hb1 r gx gsx vfxin vfro 1/4 t7504 codec z t/r + v t/r i t/r +2.4 v c r 1/2 l8574 r gx1 r rv1 c t r t1 z irp + ax v xmt l rp v rn xmt i rp pt pr v bat ts rs v bat r 1 r 2 c 1 resistor module 200 k w 200 k w 100 k w 200 w 200 w 100 k w 1 k w 1 k w the tip/ring differential current is given by: the voltage at pin xmt is given by: the component values in the ac interface of figure 12 are calculated (for the transmit and receive gains de?ed by the respective gain constants k rx and k rcv , and for the termination impedance seen in figure 11) using the following equations: note that the 200 w feed resistors contribute 400 w to the termination impedance. the termination impedance associated with the circuit in figure 12 consists of this inherent 400 w feeding impedance in parallel with: n a negative impedance, where, n a positive impedance, where, the negative and positive impedance terms are used to adjust the termination impedance from the inherent 400 w to any complex termination. i t/r 200 i rp v rn z irp ----------- ? ?? = v xmt v t/r 2 ------------- - = r rv1 100r 1 k rcv ------------------ - = r rv2 100r 2 k rcv ------------------ - = c r k rcv c 100 ------------------- - = r gx1 r gx1 r t1 + ----------------------------- - r rv1 100 ------------- 1 600 --------- - 1 r 1 -------- ? ?? = 400 w = 2 x 200 w feed resistors r gx 2 x k tx r gx1 r t1 + () = c t c 100 --------- -1 r gx1 r t1 ------------- 1 100r 1 r rv1 ------------------ - + ? ?? + = r t2 r 2 c c t -------------- - = 2 100 --------- - x r gx1 r gx1 r t1 + ----------------------------- - r t2 1 j w c t ------------- - + ? ?? ? r gx1 r t1 + r t1 ----------------------------- - ? ??
data sheet october 1998 lucent technologies inc. 31 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring ac design (continued) design equations (continued) using the circuit of figure 12, the ratio of capacitors c t and c r will affect the (transmit and receive) gain ?tness, and to a lesser degree the return loss of the line circuit. thus, depending on the requirements, c t and c r may need to be tight tolerance capacitors. if this is the case, capacitors c t and c r may be combined into a single capacitor with a looser tolerance. this is illustrated in figure 13. 12-3426.a(f).r3 figure 13. revised ac interface c t and c r combined into a single capacitor c s xmt r t2 c t irp c r v f r o r rv2 xmt r t2 irp c s = c t + c r v f r o r rv2 r rv1 r rv1 to scale c s (higher), increase c t (and decrease r t2 ) by increasing the r gx1 /(r gx1 + r t1 ) ratio by rearrang- ing the circuit in figure 13 and by adding resistor r sc from xmt to irp as shown below. 12-3427.abf) figure 14. addition of resistor r sc from xmt to irp then, once the gains and complex termination are set, if the hybrid balance network is identical to the termination impedance, then the hybrid balance is set by a single resistor (shown in figure 12) and is computed as fol- lows: the l8574 slic is ground referenced. however, a +5 v only codec, such as t7504, is referenced to +2.5 v. the l8574 slic has suf?ient dynamic range to accommo- date an ac signal from the codec that is referenced to +2.5 v without clipping distortion. furthermore, a dc current will ?w between the l8574 slic and +5 v only codec. with the l8574 slic, this current will not affect ac performance, but it does waste power. to avoid wasted power consumption, blocking capacitors can be added. capacitors should be placed to block any path from any low impedance +2.5 v biased node on the t7504 codec (or other +5 v only codec) to the slic. a blocking capacitor (c b ) has been added in the applica- tion drawing in figure 14. after the blocking capacitor c b is added, the above component values may have to be adjusted slightly to optimize performance. the effects of the blocking capacitor are best evaluated and optimized by circuit simulation. contact your lucent technologies microelectronics group account manager for information on availability of a pspice * model. * pspice is a registered trademark of microsim corporation. r t1 r sc irp c t r t2 xmt vrn r gx1 c b vf x in r gx1 r gx1 r t1 + ----------------------------- - r rv1 r sc || () 100 ------------------------------------ - 1 400 --------- - 1 r 1 --------- ? ?? r rv1 r rv1 r sc + ------------------------------ + = r hb r gx k tx k rcv ----------------------------- =
32 32 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring ac design (continued) design equations (continued) as a practical design example, design the interface for the following set of requirements: rx = 0 db tx = 0 db zt = 900 w hy = 900 w first, calculate the gain constants: ko = = 1.2247 k rcv = k o 10 rx/20 = 1.2247 x 10 0/20 = 1.2247 k tx = 10 tx/20 = 0.8165 second, calculate individual components: r rv1 = 73,487 w choose a standard value component: r rv1 = 73.2 k w r rv2 = = 0 c r = = choose r gx1 = 100 k w : r t1 = 0 c t = c t = r t2 = = 0 r gx = 2 x k tx (r gx1 + r t1 ) r gx = 2 x 0.8165 (100 k w + 0) r gx = 163.3 k w choose a standard value resistor: r gx = 165 k w r hb = r hb = therefore, for this design example, use the following values in the circuit shown in figure 12. r t1 = 0 k w r t2 = 0 r gx = 165 k w r gx1 = 100 k w r rv1 = 73.2 k w r rv2 = 0 r hb1 = 165 k w c t = c r = figure 15 is the application circuit with the above values. z t 600 ---------- - 900 600 ---------- - = 1 ko -------- 100 r x r rcv ----------------------- k rcv c 100 ---------------------- r gx1 r gx1 r t1 + -------------------------------- r rv1 100 -------------- 1 400 ---------- - 1 r 1 --------- ? ?? = 100 k w 100 k w r t1 + -------------------------------------- - 73.2 k w 100 ----------------------- 1 400 ---------- - 1 900 ---------- - ? ?? = 100 k w 100 k w r t1 + -------------------------------------- - 1.01 = c 100 ---------- - 1 r gx1 r t1 -------------- - + 1 100 r 1 r rv1 ---------------------- - + ? ?? r 2 c c t ---------------- r gx k tx k rcv ----------------------------- 165 k w 0.8165 1.2247 ----------------------------------------- - 165 k w =
lucent technologies inc. 33 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring application diagram 12-3384.c (f) figure 15. tr-57 application diagram 200 w 200 w pta prb pra v rng v bat2 fgnd v bat1 100 k w 200 k w +5 d v cca agnd v dd dgnd +5 d 0.1 m f 0.1 m f l8574c slic rcvn xmt tip ring pt ts pr 600 w rs v bf rsw 33 nf rts 0.22 m f 0.1 m f 0.01 m f cbn clim 165 k w vf r o(n) b3 b0 b2 ce b1 parallel data interface to control logic cs n s tat ircv rgbn rdo 19 16 15 14 13 12 11 9 44 1 4 gs x (n) 1/4 t7504 vf x in(n) 100 k w 73.2 k w 20 k w 165 k w k1 17 18 2, 36 2, 27, 35 ringing supply 19.6 k w 10 m f 20 v 27 23, 34 22 7 8 38 40 19.6 k w 0.47 m f + v fx 0.1 m f 100 k w 200 k w 1 k w 1 k w 1 m w 41 42 31 30 43 25 21 20 33 3 9.53 k w 301 k w 1 m w 5.11 k w dg v fx d speed f1 f2 resistor network resistor network c vbat 0.1 m f
34 lucent technologies inc. data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring outline diagram 44-pin plcc dimensions are in millimeters. 5-2506 (c) r07 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
lucent technologies inc. 35 data sheet october 1998 relay, and protector (srp) for long loop and tr-57 applications L8574D resistive subscriber line interface circuit (slic), ring ordering information device part no. description package comcode lucL8574Dp-d resistive slic, ring relay, and protector for long loop and tr-57 applications 44-pin plcc (dry-bagged) 107874794 lucL8574Dp-dt resistive slic, ring relay, and protector for long loop and tr-57 applications 44-pin plcc (tape and reel, dry-bagged) 107840688
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ?1998 lucent technologies inc. all rights reserved printed in u.s.a. october 1998 ds98-434alc (replaces ds98-066alc) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (bracknell), france: (33) 1 41 45 77 00 (paris), sweden: (46) 8 600 7070 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 2 6608131 (milan), spain: (34) 1 807 1441 (madrid)

▲Up To Search▲

Price & Availability of L8574D

	To Download L8574D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .